From: Andrea Mazzoleni (am@mediacom.it)
Date: Mon 29 Apr 2002 - 17:09:25 IDT
The PLL N divider is sometimes computed incorrectly. For example with this modeline : 21.2784 416 424 488 520 312 318 320 341 -hsync -vsync doublescan and with this PLL data (from my GeForge board): p_min=0 p_max=4 m_min=7 m_max=13 pllfreq 14318 maxvclock 350000 the values computed by the NV3ClockSelect function are : m=13 n=309 p=4 There N is out of the 8 bit allowed range. This patch fix the problem : diff -u /mame/svgalib/drivers/nv3.c drivers/nv3.c --- /mame/svgalib/drivers/nv3.c Sat Apr 27 11:52:52 2002 +++ drivers/nv3.c Mon Apr 29 14:51:24 2002 @@ -805,7 +805,7 @@ nMax=(int) (((MAXVCLOCK/PLL_INPUT_FREQ)*fm)-0.5); nMin=(int) (((128000/PLL_INPUT_FREQ)*fm)+0.5); n=(int)(((clockIn*((float)(1<<p)))/PLL_INPUT_FREQ)*fm); - if(n>=nMin && n<=nMax) { + if(n>=nMin && n<=nMax && n<256) { float fn=(float)n; target=(PLL_INPUT_FREQ*(fn/fm))/((float)(1<<p)); diff=fabs(target-clockIn); -- Andrea Mazzoleni 935A 2D3C 5C70 BCD6 CB0C ED89 7C19 4321 6340 3F6D ------------------------------------------------------------------ Unsubscribe: To: listbot@svgalib.org Body: unsubscribe linux-svgalib
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